18-743 Project: Low Power AES Implementations

This report presents low power hardware implementations of the advanced encryption standard (AES). The low power circuit level designs will be implemented in a 65nm CMOS process from STMicroelectronics. There will be a synthesized low power base design for comparison purposes using general purpose standard VT (GPSVT) gate libraries. For comparison, the gate libraries of the base design will be changed to general purpose high VT (GPHVT), low power standard VT (LPSVT) and low power high VT (LPHVT) gate libraries. A burst mode design will also be implemented and compared. If time allows, further designs will be investigated as well. The low power implementations will be either synthesized using the Synopsys Design Compiler tool or will be designed fully custom on the Cadence Virtuoso tool, using GPSVT, GPHVT, LPSVT or LPHVT gate libraries. The focus of the project will be on low power AES-128 encryption. The keys required for the encryption will be supplied on the fly. After the synthesized and custom designs, the low power implementations will be compared to the base design implementation with respect to their performance and energy. The comparison of different low power circuit level implementations will be useful for future low power AES research and low power AES hardware implementations.